1. Field of the Invention
The present invention relates to a chip-packaging, and more particularly, to a chip-packaging with bonding options having a plurality of package substrates.
2. Description of the Prior Art
In the modern VLSI circuit design, circuits in a package are connected to an outside power supply or other devices by a bonding mechanism. Therefore, allocations of bonding pads and methods of bonding options are basic and important technologies. In general, there are many different functions in one circuit, and there are many pins corresponding to the different functions in a circuit package. However, not all functions of the circuit are used, so some pins in the circuit package are connected to the outside circuits while others are not. Thus, some pins called Enable and Disable are provided. Pins having the function of Enable mean that when the pins are given a fixed high voltage (usually the voltage of the power supply), some functions corresponding to these pins in the chip are enabled. Similarly, pins having the function of Disable mean that some functions of the chip are disabled when the pins are given a fixed low voltage (usually the GND voltage). The Enable pins and the Disable pins allow make users to be able to choose the different functions of the chip so as to increase efficiency of the chip.
The method of providing a bonding option is used to provide Enable, Disable, and Input/Output options for some pins of a package. This method not only allows users to change the hardware configuration of VLSI circuits, but also to provide detecting and debugging of the VLSI circuits.
In the prior art, one bonding option usually comprises a plurality of bonding pads. These bonding pads provide different bonding choices. For example, a bonding pad can be connected to a high voltage pin (supply voltage) or a low voltage pin (ground). Previous architectures of the bonding options include two types: the value-default type and the power/ground proximity type. Please refer to FIG. 1 and FIG. 2. FIG. 1 and FIG. 2 illustrate an architecture of the bonding option of the value-default type. In the architecture, each bonding pad has been connected to a logic “1” of a high voltage or a logic “0” of a low voltage in the bonding option circuitry. If there is not any input signal applied to the pin of the bonding pad, the voltage of the pin will maintain a default voltage, which depends on what the pin is connected to. For example, the default voltage is high voltage “1” in the bonding option of the value-default type of FIG. 1. If the voltage of the pin is not defined by an outside system, the pin has logic “1”. On the other hand, the default voltage is low voltage “0” in the bonding option of the value-default type of FIG. 2, and thus if the voltage of the pin is not defined by an outside system, the pin has logic “0”.
Here we further state the principle of operations in FIG. 1 and FIG. 2. Please refer to FIG. 1. The bonding option device 12 of the value-default type in FIG. 1 comprises a passive circuit 10. The passive circuit 10 that is connected to POWER and the power supply consists of a PMOS. The passive circuit 10 has small resistance so that it has really high conductivity. When the passive circuit 10 turns on, the voltage drop between the drain and the source of the PMOS is almost zero. Therefore, POWER is set to the voltage of the power supply. In other words, when POWER is not input by outside signals, the passive circuit 10 turns on and POWER increases to a high voltage so that the inside circuitry will receive a signal of logic “1” from the bonding pad.
Please refer to FIG. 2. The bonding option device 16 of the value-default type in FIG. 2 comprises a passive circuit 14. The passive circuit 10 that is connected to GND and the ground consists of a NMOS. The passive circuit 14 also has small resistance so that it has considerably high conductivity. When the passive circuit 14 turns on, the voltage drop between the drain and the source of the NMOS is almost zero. Therefore, GND is set to the voltage of the ground. Say, when GND is not applied by outside signals, the passive circuit 14 turns on and GND is forced to a low voltage so that the inside circuitry will receive a signal of logic “0” from the bonding pad.
However, the architecture has undesirable disadvantages. If one bonding pad of the architecture is applied by an input signal from an outside system and the input signal is different from the default voltage, it leads to additional power consumption. This disadvantage is serious in the modern electronic devices of small sizes.
Please refer to FIG. 3. FIG. 3 illustrates the well-known architecture 19 of the bonding option of the power/ground proximity type. The architecture comprises a plurality of bonding pads, and each bonding pad is adjacent to a POWER and a GND. These bonding pads do not have a default voltage. If one bonding pad must be connected to logic “1”, the bonding pad is connected to POWER in FIG. 3. If one bonding pad must be connected to logic “0”, the bonding pad is connected to GND. The architecture not only provides logic “1” or “0” for bonding pads but also avoids power waste. However, as described before, each bonding pad needs two connection points, POWER and GND for bonding choices, so these connection points and each bonding pad should be specially arranged. In the case of a chip with many pins, arrangement of the bonding pads becomes very troublesome.